? BCM1280 dual-core 64-bit mips ? processor with spi-4/ht (new!) ? two 64-bit mips ? cpus, scalable from 800 mhz?1.2 ghz quad issue in-order pipeline with dual-execute and dual- memory pipes enhanced skew pipeline enables a zero load-to-use penalty 32-kb instruction cache and 32-kb data cache (ecc protected) fast on-chip multiprocessor bus connects the cpus, l2 cache, memory controller, and i/o bridges runs at half the cpu core frequency and is 256 bits wide on-chip l2 cache 1 mb shared by two cpus and i/o agents eight-way associative, ecc protected any way can be programmed as fast on-chip ram ddr memory controller memory bandwidth as high as 100 gbps configurable as 2x64-bit or 4x32-bit wide channels runs up to 400-mhz clock rate, 800-mhz data rate support for ddr, ddr2, and fcram three independent, 19.2 full-duplex ports configurable as 16/8-bit hypertransport? (ht) or channelized oif spi-4 phase 2 runs up to 600 mhz ddr for aggregate bandwidth of 38.4 gbps per port includes intelligent hash and filter engine on each port to route packets supports glueless connectivity of multiple BCM1280 devices to build a distributed shared-memory system with hardware- based coherency on-chip switch connects multiprocessor bus to high-speed interfaces 256-gbps bisection bandwidth supports both packet transfer and memory transactions integrated network and system i/o four gigabit-ethernet macs configurable as packet fifo interfaces 64-bit pci-x interface at 133 mhz generic i/o for direct connect to boot rom, flash memory two smbus serial configuration interfaces pcmcia control interface and up to 16 interrupts four uart interfaces on-chip debug capability ejtag bus trace unit (internal logic analyzer) support for leading operating systems, including vxworks ? , linux ? , qnx ? , and netbsd evaluation board platform available with samples (includes tools, firmware, and software drivers) industry-leading performance 2.5 dhrystone mips/mhz per cpu 10 million packets per second of l3 forwarding 128 gbps (@ 1.0 ghz) on-chip bus bandwidth, with 100 gbps memory bandwidth and 145 gbps 1/0 bandwidth low-power dissipation of 17w @ 1 ghz high functional integration, reducing overall system cost programming ease and flexibility based on mips64? instruction set architecture (isa) software compatible with bcm1250 and bcm112x broad tools and system software support features summary of benefits applications because of its world-class performance, power efficiency, and integration, the BCM1280 processor is ideal for a broad variety of applications, including: enterprise-class routers and switches multifunction security platforms (vpn/ssl/ids) high-end raid arrays san routers/gateways/switches wireless infrastructure plat forms (e.g., rnc, ggsn, msc) BCM1280 fabric interface spi-4.2 spi-4.2 ht or spi-4.2 cpu expansion asic or npu x multiservice card
overview ? phone: 949-450-8700 fax: 949-450-8710 e-mail: info@broadcom.com web: www.broadcom.com broadcom corporation 16215 alton parkway, p.o. box 57013 irvine, california 92619-7013 ? 2004 by broadcom corporation. all rights reserved. 1280-pb01-r 09/30/04 broadcom ? , the pulse logo, and connecting everything ? are trademarks of broadcom corporation and/ or its subsidiaries in the united states and certain ot her countries. all other trademarks are the property of their respective owners. the BCM1280 device is an mips64 processor core-based system-on-a- chip (soc) that offers industry-leading performance, high functional integration, and low-power levels required by next-generation computing, storage, and networking applications. the BCM1280 is a scalable chip multiprocessor (cmp) system consisting of two broadcom sb-1 high-performance mips64 cpus, a shared 1-mb l2 cache, a ddr memory controller, and integrated i/o. all major blocks of the processor are connected together via the zbbus, a high-speed, split-transaction multiprocessor bus. the bus implements the standard mesi protocol to ensure coherency between the two cpus, l2 cache, i/o agents, and memory. in addition, the BCM1280 supports an interchip ccnuma protocol for cache coherent distributed shared memory systems. the three high-speed ht ports provide interchip communications to other BCM1280 processors or to ht bridging i/o chips. each port can optionally be configured as an spi-4 phase 2 packet interface for connectivity to 10 gbps network devices. four gigabit- ethernet macs (10/100/1000) enable easy interfacing to lans or control backplanes. to enable higher data rates (or in cases where ethernet protocol processing is not required), the gigabit-ethernet macs can be configured as 8-bit and/or 16-bit packet fifos. the BCM1280 also integrates a 64-bit, 133-mhz pci-x local bus for direct connection to i/o devices. four se rial ports are available for use as uarts for console ports. to enable low-chip count systems, the BCM1280 also includes a configurable generic bus that allows glueless connection of a boot rom or flash memory and simple i/o peripherals. on-chip debug, trace, and performance monitoring functions assist both hardware and software designers in debugging and tuning the system. the system can be run in either big-endian or little-endian mode. implementation of mips64 isa the sb-1 cpu core is a high-performance implementation of the standard mips64 isa that incorporates the mips-3d and mips-mdmx application-specific extensions (a ses). the core supports a 4-issue enhanced skew pipeline and can di spatch up to two memory and two alu (integer, floating point, mdmx, or mips-3d) instructions per cycle. 100 gbps 8 gps 4x gmii 8b/16b fifo ddr memory controller zbbus tm 256 bits 1 mb l2 cache generic bus & flash i/o ? core clock; 128 gbps @ 1 ghz 64-bit pci-x dual smbus jtag sb -1 core gpio/ interrupt/ pcmcia data mover debug/ bus trace serial interfaces 10/100/ 1000 mac fifo dma 10/100/ 1000 mac dma 10/100/ 1000 mac dma 10/100/ 1000 mac dma packet dma memory bridge x spi-4 ht spi-4 ht 3x spi - 4.2/ht (19.2 gbps each direction) spi-4 ht spi-4 ht sb-1 core next generation broadband processors bcm1255 BCM1280 bcm1455 bcm1480 # of cpus 2 244 l2 cache 512 kb 1 mb 1 mb 1 mb ddr2 support yes yes yes yes # of macs 4 gmii 4 gmii 4 gmii 4 gmii pci-x 1 x 64-bit 1 x 64-bit 1 x 64-bit 1 x 64-bit # of spi-4/ht ports 0 303
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